SH7263 Datasheet, PDF (1204/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 22 A/D Converter (ADC)
Table 22.5 A/D Conversion Time (Multi Mode and Scan Mode)
CKS1
CKS0
Conversion Time (States)
0
0
128 (constant)
1
256 (constant)
1
0
512 (constant)
Note: Values in the table are the numbers of states.
22.4.6 External Trigger Input Timing
A/D conversion can also be externally triggered. When the TRGS[3:0] bits in ADCSR are set to
B'1001, an external trigger is input to the ADTRG pin. The ADST bit in ADCSR is set to 1 at the
falling edge of the ADTRG pin, thus starting A/D conversion. Other operations, regardless of the
operating mode, are the same as when the ADST bit has been set to 1 by software. Figure 22.6
shows the timing.
Pφ
ADTRG
Internal trigger
signal
ADST
A/D conversion
Figure 22.6 External Trigger Input Timing
Rev. 2.00 Mar. 14, 2008 Page 1170 of 1824
REJ09B0290-0200