SH7263 Datasheet, PDF (1226/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 24 AND/NAND Flash Memory Controller (FLCTL)
Initial
Bit
Bit Name Value R/W Description
17
QTSEL 0
R/W Select Dividing Rates for Flash Clock
Selects the dividing rate of clock FCLK in the flash
memory. This bit is used together with FCKSEL.
• QTSEL = 0, FCKSEL = 0: Divides a clock (Pφ)
provided from the CPG by two and uses it as FCLK.
• QTSEL = 0, FCKSEL = 1: Uses a clock (Pφ)
provided from the CPG as FCLK.
• QTSEL = 1, FCKSEL = 0: Divides a clock (Pφ)
provided from the CPG by four and uses it as FCLK.
• QTSEL = 1, FCKSEL = 1: Setting prohibited
16
—
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
15
FCKSEL 0
R/W Flash Clock Select
Selects the dividing rate of clock FCLK in the flash
memory. This bit is used together with QTSEL. Refer to
the description of QTSEL.
14
—
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
13, 12 ECCPOS 00
[1:0]
R/W ECC Position Specification 1 and 0
Specify the position (0/4th/8th byte) to place the ECC in
the control code area.
00: Places the ECC at the 0 to 7th byte of control code
area
01: Places the ECC at the 4th to 11th byte of control
code area
10: Places the ECC at the 8th to 15th byte of control
code area
11: Setting prohibited
Rev. 2.00 Mar. 14, 2008 Page 1192 of 1824
REJ09B0290-0200