SH7263 Datasheet, PDF (519/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
11.3.7 Timer Input Capture Control Register (TICCR)
TICCR is an 8-bit readable/writable register that specifies input capture conditions when TCNT_1
and TCNT_2 are cascaded. The MTU2 has one TICCR in channel 1.
Bit: 7
6
5
4
3
2
1
0
-
-
-
-
I2BE I2AE I1BE I1AE
Initial value: 0
0
0
0
0
0
0
0
R/W: R R R R R/W R/W R/W R/W
Initial
Bit
Bit Name Value R/W Description
7 to 4 —
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
3
I2BE
0
R/W Input Capture Enable
Specifies whether to include the TIOC2B pin in the
TGRB_1 input capture conditions.
0: Does not include the TIOC2B pin in the TGRB_1
input capture conditions
1: Includes the TIOC2B pin in the TGRB_1 input
capture conditions
2
I2AE
0
R/W Input Capture Enable
Specifies whether to include the TIOC2A pin in the
TGRA_1 input capture conditions.
0: Does not include the TIOC2A pin in the TGRA_1
input capture conditions
1: Includes the TIOC2A pin in the TGRA_1 input
capture conditions
1
I1BE
0
R/W Input Capture Enable
Specifies whether to include the TIOC1B pin in the
TGRB_2 input capture conditions.
0: Does not include the TIOC1B pin in the TGRB_2
input capture conditions
1: Includes the TIOC1B pin in the TGRB_2 input
capture conditions
Rev. 2.00 Mar. 14, 2008 Page 485 of 1824
REJ09B0290-0200