SH7263 Datasheet, PDF (848/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 16 Synchronous Serial Communication Unit (SSU)
16.4.6 SCS Pin Control and Conflict Error
When bits CSS1 and CSS0 in SSCRH are specified to B'10 and the SSUMS bit in SSCRL is
cleared to 0, the SCS pin functions as an input (Hi-Z) to detect a conflict error. A conflict error
detection period is from setting the MSS bit in SSCRH to 1 to starting serial transfer and after
transfer ends. When a low level signal is input to the SCS pin within the period, a conflict error
occurs. At this time, the CE bit in SSSR is set to 1 and the MSS bit is cleared to 0.
Note: While the CE bit is set to 1, transmission or reception is not resumed. Clear the CE bit to 0
before resuming the transmission or reception.
External input to SCS
Internal-clocked SCS
MSS
Internal signal for
transfer enable
CE
Data written
to SSTDR
SCS output
(Hi-Z)
Conflict error
detection period
Worst time for
internally clocking SCS
Figure 16.10 Conflict Error Detection Timing (Before Transfer)
Pφ
SCS
(Hi-Z)
MSS
Internal signal for
transfer enable
CE
Transfer
end
Conflict error detection
period
Figure 16.11 Conflict Error Detection Timing (After Transfer End)
Rev. 2.00 Mar. 14, 2008 Page 814 of 1824
REJ09B0290-0200