SH7263 Datasheet, PDF (1251/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 24 AND/NAND Flash Memory Controller (FLCTL)
24.4.4 Command Access Mode
Command access mode accesses flash memory by specifying a command to be issued to flash
memory, address, data, read/write direction, and number of times to the registers. In this mode, I/O
data can be transferred by the DMA via FLDTFIFO.
(1) AND-Type Flash Memory Access
Figures 24.4 and 24.5 show examples of read operation for AND-type flash memory. In these
examples, the first command is specified as H'00 and address data length is specified as 2 bytes
(SA1 and SA2). (Only SA1 and SA2 are specified, while CA1 and CA2 are not specified.). In
addition, the number of read bytes is specified as 4 bytes in the data counter and H'FF is specified
as the second command.
OE
WE
CDE
SC
I/O7 to I/O0
R/B
H'00
SA1 SA2
1234
Figure 24.4 Read Operation Timing for AND-Type Flash Memory (1)
OE
WE
CDE
SC
I/O7 to I/O0
R/B
H'FF
Figure 24.5 Read Operation Timing for AND-Type Flash Memory (2)
Rev. 2.00 Mar. 14, 2008 Page 1217 of 1824
REJ09B0290-0200