SH7263 Datasheet, PDF (1007/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Bit3: TSR3
0
1
Section 19 Controller Area Network (RCAN-TL1)
Description
Timer Compare Match has not occurred to the TCMR2 (Initial value)
[Clearing condition] Writing ‘1’ to IRR11 (Timer Compare Match Interrupt 1)
Timer Compare Match has occurred to the TCMR2
[Setting condition]
TCMR2 matches to Cycle Time (TCMR2 = CYCTR), if TTCR0 bit12 = 1.
Bit 2 — Timer Compare Match Flag 1 (TSR2): Indicates that a Compare-Match condition
occurred to the Timer Compare Match Register 1 (TCMR1). When the value set in the TCMR1
matches to Cycle Time Register (TCMR1 = CYCTR), this bit is set if TTCR0 bit11 = 1. Please
note that this bit is read-only and is cleared when IRR15 (Timer Compare Match Interrupt 1) is
cleared.
Bit2: TSR2
0
1
Description
Timer Compare Match has not occurred to the TCMR1 (Initial value)
[Clearing condition] Writing ‘1’ to IRR15 (Timer Compare Match Interrupt 1)
Timer Compare Match has occurred to the TCMR1
[Setting condition]
TCMR1 matches to Cycle Time (TCMR1 = CYCTR), if TTCR0 bit11 = 1.
Bit 1 — Timer Compare Match Flag 0 (TSR1): Indicates that a Compare-Match condition
occurred to the Compare Match Register 0 (TCMR0). When the value set in the TCMR0 matches
to the Timer value (TCMR0 = TCNTR), this bit is set if TTCR0 bit10 = 1. Please note that this bit
is read-only and is cleared when IRR14 (Timer Compare Match Interrupt 0) is cleared.
Bit1: TSR1
0
1
Description
Compare Match has not occurred to the TCMR0 (Initial value)
[Clearing condition] Writing ‘1’ to IRR14 (Timer Compare Match Interrupt 0)
Compare Match has occurred to the TCMR0
[Setting condition] TCMR0 matches to the Timer value (TCMR0 = TCNTR)
Bit 0 — Timer Overrun/Next_is_Gap Reception/Message Error (TSR0): This flag is assigned
to three different functions. It indicates that the Timer has overrun when working in event-trigger
mode, time reference message with Next_is_Gap set has been received in time-trigger mode, and
error detected on the CAN bus has occurred in test mode, respectively. Test mode has higher
priority with respect to the other settings.
Rev. 2.00 Mar. 14, 2008 Page 973 of 1824
REJ09B0290-0200