SH7263 Datasheet, PDF (1279/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 25 USB 2.0 Host/Function Module (USB)
Table 25.4 Test Mode Operation
Test Mode
Normal operation
Test_J
Test_K
Test_SE0_NAK
Test_Packet
Reserved
UTST Bit Setting
Functions of Function
Controller Selected
Functions of Host Controller
Selected
0000
0000
0001
1001
0010
1010
0011
1011
0100
1100
0101 to 0111
1101 to 1111
25.3.5 FIFO Port Configuration Registers (CFBCFG, D0FBCFG, D1FBCFG)
CFBCFG, D0FBCFG, and D1FBCFG are registers that control FIFO port accesses. There are
three FIFO ports; CPU-FIFO, DMA0-FIFO, and DMA1-FIFO. Accesses to these ports are
controlled by the corresponding configuration registers.
These registers are initialized by a power-on reset.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
- TENDE FEND -
-
-
-
FWAIT[3:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
R/W: R
R
R
R
R
R R/W R/W R
R
R
R RW R/W R/W R/W
Bit
Bit Name
15 to 10 ⎯
9
TENDE
Initial
Value
All 0
0
R/W
R
R/W
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
DMA Transfer End Sampling Enable
Controls the acceptance of a DMA transfer end
signal sent from the direct memory access controller
(DMAC) at the end of DMA transfer.
0: A DMA transfer end signal is not sampled.
1: A DMA transfer end signal is sampled.
Rev. 2.00 Mar. 14, 2008 Page 1245 of 1824
REJ09B0290-0200