SH7263 Datasheet, PDF (275/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 9 Bus State Controller (BSC)
Initial
Bit
Bit Name Value R/W Description
3, 2
⎯
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
1
HIZMEM 0
R/W High-Z Memory Control
Specifies the pin state in software standby mode or
deep standby mode for A25 to A0, BS, CSn, CS2x,
RD/WR, WEn/DQMxx/AH, RD, and FRAME. At bus-
released state, these pin are high-impedance states
regardless of the setting value of the HIZMEM bit.
0: High impedance in software standby mode or deep
standby mode.
1: Driven in software standby mode or deep standby
mode
0
HIZCNT* 0
R/W High-Z Control
Specifies the state in software standby mode, deep
standby mode, or bus-released state for CKE, RASU,
RASL, CASU, and CASL.
0: High impedance in software standby mode, deep
standby mode, or bus-released state for CKE,
RASU, RASL, CASU, and CASL.
1: Driven in software standby mode, deep standby
mode, or bus-released state for CKE, RASU, RASL,
CASU, and CASL.
Note: * For High-Z control of CKIO, see section 4, Clock Pulse Generator (CPG).
Rev. 2.00 Mar. 14, 2008 Page 241 of 1824
REJ09B0290-0200