SH7263 Datasheet, PDF (421/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 10 Direct Memory Access Controller (DMAC)
Figure 10.1 shows the block diagram of the DMAC.
On-chip
memory
On-chip
peripheral module
Iteration
control
Register
control
DMA transfer request signal
DMA transfer acknowledge signal
Interrupt controller
Start-up
control
HEIn
DEIn
Request
priority
control
External ROM
External RAM
External device
(memory mapped)
External device
(with acknowledge)
Bus
interface
Bus state
controller
RDMATCRn
DMATCRn
RSARn
SARn
RDARn
DARn
CHCRn
DMAOR
DMARS0
to DMARS3
DMAC module
DREQ0 to DREQ3
DACK0 to DACK3,
TEND0, TEND1
[Legend]
RDMATCR: DMA reload transfer count register
DMATCR: DMA transfer count register
RSAR: DMA reload source address register
SAR:
DMA source address register
RDAR: DMA reload destination address register
DAR:
DMA destination address register
CHCR:
DMA channel control register
DMAOR:
DMA operation register
DMARS0 to DMARS3: DMA extension resource selectors 0 to 3
HEIn:
DMA transfer half-end interrupt request to the CPU
DEIn:
DMA transfer end interrupt request to the CPU
n = 0 to 7
Figure 10.1 Block Diagram of DMAC
Rev. 2.00 Mar. 14, 2008 Page 387 of 1824
REJ09B0290-0200