SH7263 Datasheet, PDF (430/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 10 Direct Memory Access Controller (DMAC)
Initial
Bit
Bit Name Value R/W Description
29
RLDSAR 0
R/W SAR Reload Function ON/OFF
Enables (ON) or disables (OFF) the function to reload
SAR and DMATCR.
0: Disables (OFF) the function to reload SAR and
DMATCR
1: Enables (ON) the function to reload SAR and
DMATCR
28
RLDDAR 0
R/W DAR Reload Function ON/OFF
Enables (ON) or disables (OFF) the function to reload
DAR and DMATCR.
0: Disables (OFF) the function to reload DAR and
DMATCR
1: Enables (ON) the function to reload DAR and
DMATCR
27
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
26
DAF
0
R/W Fixed Destination Address 16-Byte Transfer
Enabled when the transfer size (set in TS[1:0]) is 16
bytes and the destination address mode (set in
DM[1:0]) is fixed address.
0: 16 bytes of data are transferred from the address
specified in DAR.
1: Four bytes of data are transferred four times from
the address specified in DAR. This function is
exclusively for use with the ROM-DEC.
25
SAF
0
R/W Fixed Source Address 16-Byte Transfer
Enabled when the transfer size (set in TS[1:0]) is 16
bytes and the source address mode (set in SM[1:0]) is
fixed address.
0: 16 bytes of data are transferred from the address
specified in SAR.
1: Four bytes of data are transferred four times from
the address specified in SAR. This function is
exclusively for use with the ROM-DEC.
Rev. 2.00 Mar. 14, 2008 Page 396 of 1824
REJ09B0290-0200