SH7263 Datasheet, PDF (1478/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 27 Sampling Rate Converter (SRC)
Initial
Bit
Bit Name Value R/W Description
6, 5
⎯
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
4
FLF
0
R
Flush Processing Status Flag
Indicates whether flush processing is in progress or
not.
[Clearing conditions]
• When flush processing has been completed.
• When 1 has been written to the CL bit in
SRCCTRL.
• When 1 has been written to the SRCEN bit in
SRCCTRL while SRCEN is 0.
[Setting condition]
• When 1 has been written to the FL bit in
SRCCTRL.
3
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
2
OVF
0
R/(W)* Output Data FIFO Overwrite Interrupt Request Flag
Indicates that the sampling rate conversion for the
next data has been completed when there are eight
units of data in the output FIFO. The conversion is
stopped until the OVF flag is cleared.
[Clearing condition]
• When 0 has been written to the OVF bit after
reading OVF = 1.
• When 1 has been written to the CL bit in
SRCCTRL.
• When 1 has been written to the SRCEN bit in
SRCCTRL while SRCEN is 0.
[Setting condition]
• When the sampling rate conversion for the next
data has been completed when there are eight
units of data in the output FIFO.
Rev. 2.00 Mar. 14, 2008 Page 1444 of 1824
REJ09B0290-0200