SH7263 Datasheet, PDF (1654/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 34 List of Registers
Module
Name Register Name
Abbreviation
ROM-
DEC
Post-ECC correction subheader:
channel number (byte 21) data
register
SHEAD25
Post-ECC correction subheader: SHEAD26
sub-mode (byte 22) data register
Post-ECC correction subheader: SHEAD27
data type (byte 23) data register
Automatic buffering setting control CBUFCTL0
register
Automatic buffering start sector
setting:
minutes control register
CBUFCTL1
Automatic buffering start sector
setting:
seconds control register
CBUFCTL2
Automatic buffering start sector
setting:
frames control register
CBUFCTL3
ISY interrupt source mask control CROMST0M
register
CD-ROM decoder reset control
register
ROMDECRST
CD-ROM decoder reset status
register
RSTSTAT
SSI data control register
SSI
Interrupt flag register
INTHOLD
Interrupt source mask control
register
INHINT
CD-ROM decoder stream data
input register
STRMDIN0
CD-ROM decoder stream data
input register
STRMDIN2
CD-ROM decoder stream data
output register
STRMDOUT0
Number
of Bits Address
8
H'FFFC202D
Access
Size
8
8
H'FFFC202E 8
8
H'FFFC202F 8
8
H'FFFC2040 8
8
H'FFFC2041 8
8
H'FFFC2042 8
8
H'FFFC2043 8
8
H'FFFC2045 8
8
H'FFFC2100 8
8
H'FFFC2101 8
8
H'FFFC2102 8
8
H'FFFC2108 8
8
H'FFFC2109 8
16
H'FFFC2200 16, 32
16
H'FFFC2202 16
16
H'FFFC2204 16, 32
Rev. 2.00 Mar. 14, 2008 Page 1620 of 1824
REJ09B0290-0200