SH7263 Datasheet, PDF (1820/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Main Revisions for this Edition
Item
10.3.4 DMA Channel
Control Registers
(CHCR)
Page
395
10.5.3 Notice about 439
using external request
mode
10.5.4 Notice about 440
using on-chip peripheral
module request mode or
auto-request mode
11.3 Register
450
Descriptions
Table 11.3 Register
Descriptions
11.3.8 Timer
⎯
Synchronous Clear
Register (TSYCR)
11.4.2 Synchronous 521
Operation
Revision (See Manual for Details)
Table amended
Bit
Bit Name
31
TC
Newly added
Initial
Value
0
R/W Description
R/W Transfer Count Mode
Specifies whether to transmit data once or for the
count specified in DMATCR by one transfer request.
This function is valid only in on-chip peripheral module
request mode. Note that when this bit is set to 0, the
TB bit must not be set to 1 (burst mode). When the
SCIF, IIC3, SSI, SRC, SDHI, FLCTL, or SSU is
selected for the transfer request source, this bit (TC)
must not be set to 1.
0: Transmits data once by one transfer request
1: Transmits data for the count specified in DMATCR
by one transfer request
Newly added
Table amended
Channel Register Name
Abbrevia-
tion
R/W
Common Timer dead time enable
TDER
to 3 and register
4
Timer waveform control register TWCR
R /W
R/W
Timer output level buffer
register
TOLBR R/W
Initial
value
H'01
H'00
H'00
Address
H'FFFE4234
Access
Size
8
H'FFFE4260 8
H'FFFE4236 8
Deleted
Description deleted
Channels 0 to 4 can all be designated for synchronous
operation.
Rev. 2.00 Mar. 14, 2008 Page 1786 of 1824
REJ09B0290-0200