SH7263 Datasheet, PDF (1835/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Main Revisions for this Edition
Item
Page
25.3.7 FIFO Port Select 1253
Registers (CFIFOSEL,
D0FIFOSEL,
D1FIFOSEL)
(2) D0FIFOSEL,
D1FIFOSEL
25.3.8 FIFO Port
Control Registers
(CFIFOCTR,
D0FIFOCTR,
D1FIFOCTR)
1253
1254
Revision (See Manual for Details)
Note added
Notes: 1. Only reading 0 and writing 1 are valid.
2. Changing the values of the CURPIPE bits in
succession requires an access cycle lasting a
minimum of 120 ns plus five bus cycles.
Bit table amended
Table amended
Bit: 15 14
BVAL BCLR
Initial value: 0
0
R/W: R/W*¹ R/W*²
Bit
Bit Name
14
BCLR
11 to 0 DTLN[11:0]
Initial
Value
0
H'000
R/W
R/W*²
R
Description
CPU Buffer Clear*³
This bit should be used to clear the buffer with this bit
with the pipe invalid state by the pipe configuration
(PID = NAK).
0: Invalid
1: Clears the buffer memory on the CPU side.
Receive Data Length*⁴
The length of the receive data can be confirmed.
Notes amended
Notes: 1. Only 1 can be written to.
2. Only reading 0 and writing 1 are valid.
3. The BCLR bit is only valid for the buffer memory on
the CPU side when a pipe other than DCP has
been selected. Set BCLR to 1 after confirming that
FRDY is 1. When DCP is selected as a pipe, the
buffer memory on the SIE side is also cleared. In
this case, confirming that FRDY = 1 is not
necessary.
4. The DTLN bits are only valid for the buffer memory
on the CPU side. Confirm that FRDY = 1 before
checking the DTLN bit.
Rev. 2.00 Mar. 14, 2008 Page 1801 of 1824
REJ09B0290-0200