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| SH7263 Datasheet, PDF (382/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series | |||
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Section 9 Bus State Controller (BSC)
CKIO
Tp
Tpw
Trr
Trc
PALL
REF
Trc
Trr
Trc
REF
Trc Tmw Tnop
MRS
A25 to A0
A12/A11*1
CSn
RASL, RASU
CASL, CASU
RD/WR
DQMxx
D31 to D0
Hi-Z
BS
DACKn*2
Notes: 1. Address pin to be connected to pin A10 of SDRAM.
2. The waveform for DACKn is when active low is specified.
Figure 9.32 SDRAM Mode Write Timing (Based on JEDEC)
Rev. 2.00 Mar. 14, 2008 Page 348 of 1824
REJ09B0290-0200
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