SH7263 Datasheet, PDF (133/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 4 Clock Pulse Generator (CPG)
Section 4 Clock Pulse Generator (CPG)
This LSI has a clock pulse generator (CPG) that generates an internal clock (Iφ), a peripheral clock
(Pφ), and a bus clock (Bφ). The CPG consists of a crystal oscillator, PLL circuits, and divider
circuits.
4.1 Features
• Four clock operating modes
The mode is selected from among the four clock operating modes based on the frequency
range to be used and the input clock type: the clock from crystal resonator, the external clock
or the clock for USB.
• Three clocks generated independently
An internal clock (Iφ) for the CPU and cache; a peripheral clock (Pφ) for the on-chip
peripheral modules; a bus clock (Bφ = CKIO) for the external bus interface
• Frequency change function
Internal and peripheral clock frequencies can be changed independently using the PLL (phase
locked loop) circuits and divider circuits within the CPG. Frequencies are changed by software
using frequency control register (FRQCR) settings.
• Power-down mode control
The clock can be stopped in sleep mode, software standby mode, and deep standby mode, and
specific modules can be stopped using the module standby function. For details on clock
control in the power-down modes, see section 32, Power-Down Modes.
Rev. 2.00 Mar. 14, 2008 Page 99 of 1824
REJ09B0290-0200