SH7263 Datasheet, PDF (301/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 9 Bus State Controller (BSC)
(3) SDRAM*
• CS2WCR
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
A2CL[1:0]
-
-
-
-
-
-
-
Initial value: 0
0
0
0
0
1
0
1
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R R/W R/W R
R
R
R
R
R
R
Initial
Bit
Bit Name Value R/W Description
31 to 11 ⎯
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
10
⎯
1
R
Reserved
This bit is always read as 1. The write value should
always be 1.
9
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
8, 7
A2CL[1:0] 10
R/W CAS Latency for Area 2
Specify the CAS latency for area 2.
00: 1 cycle
01: 2 cycles
10: 3 cycles
11: 4 cycles
6 to 0
⎯
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
Note: * If only one area is connected to the SDRAM, specify area 3. In this case, specify area 2
as normal space or SRAM with byte selection.
Rev. 2.00 Mar. 14, 2008 Page 267 of 1824
REJ09B0290-0200