SH7263 Datasheet, PDF (790/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 15 Serial Communication Interface with FIFO (SCIF)
(2) Clock Synchronous Mode
• The transmission/reception format has a fixed 8-bit data length.
• In receiving, it is possible to detect overrun errors (ORER).
• An internal or external clock can be selected as the SCIF clock source.
⎯ When an internal clock is selected, the SCIF operates using the clock of the on-chip baud
rate generator, and outputs this clock to external devices as the synchronous clock.
⎯ When an external clock is selected, the SCIF operates on the input external synchronous
clock not using the on-chip baud rate generator.
Table 15.9 SCSMR Settings and SCIF Communication Formats
SCSMR Settings
Bit 7 Bit 6 Bit 5 Bit 3
C/A CHR PE STOP Mode
0
0
0
0
Asynchronous
1
1
0
1
1
0
0
1
1
0
1
1
x
x
x
Clock
synchronous
[Legend]
x: Don't care
SCIF Communication Format
Data Length
8 bits
Parity Bit
Not set
Set
7 bits
Not set
Set
8 bits
Not set
Stop Bit Length
1 bit
2 bits
1 bit
2 bits
1 bit
2 bits
1 bit
2 bits
None
Rev. 2.00 Mar. 14, 2008 Page 756 of 1824
REJ09B0290-0200