SH7263 Datasheet, PDF(897/1862 Page) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

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SH7263 Datasheet, PDF (897/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

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Section 17 I2C Bus Interface 3 (IIC3)

17.6 Bit Synchronous Circuit

In master mode, this module has a possibility that high level period may be short in the two states

described below.

â¢ When SCL is driven to low by the slave device

â¢ When the rising speed of SCL is lowered by the load of the SCL line (load capacitance or pull-

up resistance)

Therefore, it monitors SCL and communicates by bit with synchronization.

Figure 17.22 shows the timing of the bit synchronous circuit and table 17.5 shows the time when

the SCL output changes from low to Hi-Z then SCL is monitored.

SCL monitor

timing reference

clock

Time for monitoring

SCL (on-board)

VIH

SCL

Internal SCL

Figure 17.22 Bit Synchronous Circuit Timing

Table 17.5 Time for Monitoring SCL

CKS3

CKS2

Time for Monitoring SCL*1

0

0

9 tpcyc*2

1

21 tpcyc*2

1

0

19 tpcyc*2

1

43 tpcyc*2

Notes: 1. Monitors the (on-board) SCL level after the time (pcyc) for monitoring SCL has passed

since the rising edge of the SCL monitor timing reference clock.

2. pcyc = PÏ Ã cyc

Rev. 2.00 Mar. 14, 2008 Page 863 of 1824

REJ09B0290-0200

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