SH7263 Datasheet, PDF (899/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 17 I²C Bus Interface 3 (IIC3)
17.7.5 Note on the States of Bits MST and TRN when Arbitration is Lost
When sequential bit-manipulation instructions are used to set the MST and TRS bits to select
master transmission in multi-master operation, a conflicting situation where AL in ICSR = 1 but
the mode is master transmit mode (MST = 1 and TRS = 1) may arise; this depends on the timing
of the loss of arbitration when the bit manipulation instruction for TRS is executed.
This can be avoided in either of the following ways.
• In multi-master operation, use the MOV instruction to set the MST and TRS bits.
• When arbitration is lost, check whether the MST and TRS bits are 0. If the MST and TRS bits
have been set to a value other than 0, clear the bits to 0
Rev. 2.00 Mar. 14, 2008 Page 865 of 1824
REJ09B0290-0200