SH7263 Datasheet, PDF (973/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 19 Controller Area Network (RCAN-TL1)
Bits 10 to 8 — Time Segment 2 (TSG2[2:0] = BCR1[10:8]): These bits are used to set the
segment TSEG2 (= PHSEG2) to compensate for edges on the CAN Bus with a negative phase
error. A value from 2 to 8 time quanta can be set as shown below.
Bit 10: Bit 9: Bit 8:
TSG2[2] TSG2[1] TSG2[0] Description
0
0
0
Setting prohibited (Initial value)
0
0
1
PHSEG2 = 2 time quanta (conditionally prohibited)
0
1
0
PHSEG2 = 3 time quanta
0
1
1
PHSEG2 = 4 time quanta
1
0
0
PHSEG2 = 5 time quanta
1
0
1
PHSEG2 = 6 time quanta
1
1
0
PHSEG2 = 7 time quanta
1
1
1
PHSEG2 = 8 time quanta
Bits 7 and 6: Reserved. The written value should always be ‘0’ and the returned value is ‘0’.
Bits 5 and 4 - ReSynchronisation Jump Width (SJW[1:0] = BCR0[5:4]): These bits set the
synchronisation jump width.
Bit 5:
SJW[1]
0
0
1
1
Bit 4:
SJW[0]
0
1
0
1
Description
Synchronisation Jump width = 1 time quantum (Initial value)
Synchronisation Jump width = 2 time quanta
Synchronisation Jump width = 3 time quanta
Synchronisation Jump width = 4 time quanta
Bits 3 to 1: Reserved. The written value should always be ‘0’ and the returned value is ‘0’.
Bit 0 — Bit Sample Point (BSP = BCR1[0]): Sets the point at which data is sampled.
Bit 0 : BSP
0
1
Description
Bit sampling at one point (end of time segment 1) (Initial value)
Bit sampling at three points (rising edge of the last three clock cycles of
PHSEG1)
Rev. 2.00 Mar. 14, 2008 Page 939 of 1824
REJ09B0290-0200