SH7263 Datasheet, PDF (235/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 7 User Break Controller (UBC)
Bit
Bit Name
13
SCMFD0
12
SCMFD1
11 to 7 ⎯
6
PCB1
5
PCB0
4 to 0 ⎯
Initial
Value
0
0
All 0
0
0
All 0
R/W
R/W
R/W
R
R/W
R/W
R
Description
I Bus Cycle Condition Match Flag 0
When the I bus cycle condition in the break conditions
set for channel 0 is satisfied, this flag is set to 1. In
order to clear this flag, write 0 to this bit.
0: The I bus cycle condition for channel 0 does not
match
1: The I bus cycle condition for channel 0 matches
I Bus Cycle Condition Match Flag 1
When the I bus cycle condition in the break conditions
set for channel 1 is satisfied, this flag is set to 1. In
order to clear this flag, write 0 to this bit.
0: The I bus cycle condition for channel 1 does not
match
1: The I bus cycle condition for channel 1 matches
Reserved
These bits are always read as 0. The write value
should always be 0.
PC Break Select 1
Selects the break timing of the instruction fetch cycle
for channel 1 as before or after instruction execution.
0: PC break of channel 1 is generated before
instruction execution
1: PC break of channel 1 is generated after instruction
execution
PC Break Select 0
Selects the break timing of the instruction fetch cycle
for channel 0 as before or after instruction execution.
0: PC break of channel 0 is generated before
instruction execution
1: PC break of channel 0 is generated after instruction
execution
Reserved
These bits are always read as 0. The write value
should always be 0.
Rev. 2.00 Mar. 14, 2008 Page 201 of 1824
REJ09B0290-0200