SH7263 Datasheet, PDF (714/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 13 Watchdog Timer (WDT)
13.5 Usage Notes
Pay attention to the following points when using the WDT in either the interval timer or watchdog
timer mode.
13.5.1 Timer Variation
After timer operation has started, the period from the power-on reset point to the first count up
timing of WTCNT varies depending on the time period that is set by the TME bit of WTCSR. The
shortest such time period is thus one cycle of the peripheral clock, Pφ, while the longest is the
result of frequency division according to the value in the CKS[2:0] bits. The timing of subsequent
incrementation is in accord with the selected frequency division ratio. Accordingly, this time
difference is referred to as timer variation.
This also applies to the timing of the first incrementation after WTCNT has been written to during
timer operation.
13.5.2 Prohibition against Setting H'FF to WTCNT
When the value in WTCNT reaches H'FF, the WDT assumes that an overflow has occurred.
Accordingly, when H'FF is set in WTCNT, an interval timer interrupt or WDT reset will occur
immediately, regardless of the current clock selection by the CKS[2:0] bits.
13.5.3 Interval Timer Overflow Flag
When the value in WTCNT is H'FF, the IOVF flag in WTCSR cannot be cleared.
Only clear the IOVF flag when the value in WTCNT has either become H'00 or been changed to a
value other than H'FF.
Rev. 2.00 Mar. 14, 2008 Page 680 of 1824
REJ09B0290-0200