SH7263 Datasheet, PDF (1587/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 32 Power-Down Modes
State*¹
Power-
Down
Mode
Transition
Conditions
CPG
CPU
On-Chip
RAM
(High- On-Chip
Speed) RAM
On-Chip
CPU
Cash (for Data Peripheral
Register Memory Retention) Modules RTC
Power External Canceling
supply Memory Procedure
Module
standby
mode
Set the MSTP Running Running Held
bits in
STBCR2 to
STBCR6 to 1
Running Running
Specified
module
halted
Halted
Running Auto-
• Clear MSTP
refresh
bit to 0
• Power-on
reset (only for
H-UDI, UBC
and DMAC)
Notes: 1. The pin state is retained or set to high impedance. For details, see appendix A, Pin
States.
2. RTC operates when the START bit in the RCR2 register is set to 1. For details, see
section 14, Realtime Clock (RTC).
3. Setting the bits RAMKP3 to RAMKP0 in the RAMKP register to 1 enables to retain the
data in the corresponding area on the on-chip RAM during the transition to deep
standby. However, the stored contents are initialized when deep standby mode is
canceled by a power-on reset.
4. Deep standby mode can be canceled by an interrupt (NMI or IRQ) or a reset (manual
reset or power-on reset). However, when deep standby mode is canceled by the NMI
interrupt or IRQ interrupt, power-on reset exception handling is executed instead of
interrupt exception handling. The power-on reset exception handling is executed also in
the cancellation of deep standby mode by manual reset.
5. The stored contents are initialized when software standby mode is canceled by a
power-on reset.
6. The stored contents can be retained even when software standby mode is canceled by
a power-on reset by disabling access to the on-chip RAM (high-speed) by means of the
RAME bits in the SYSCR1 register or the RAMWE bits in the SYSCR2 register.
Rev. 2.00 Mar. 14, 2008 Page 1553 of 1824
REJ09B0290-0200