SH7263 Datasheet, PDF (1600/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 32 Power-Down Modes
Initial
Bit
Bit Name Value R/W Description
7 to 4 ⎯
All 1
R
Reserved
These bits are always read as 1. The write value
should always be 1.
3
RAME3
1
R/W RAM Enable 3 (corresponding area of on-chip RAM
(high-speed): page 3*)
0: Access to on-chip RAM (high-speed) disabled
1: Access to on-chip RAM (high-speed) enabled
2
RAME2
1
R/W RAM Enable 2 (corresponding area of on-chip RAM
(high-speed): page 2*)
0: Access to on-chip RAM (high-speed) disabled
1: Access to on-chip RAM (high-speed) enabled
1
RAME1
1
R/W RAM Enable 1 (corresponding area of on-chip RAM
(high-speed): page 1*)
0: Access to on-chip RAM (high-speed) disabled
1: Access to on-chip RAM (high-speed) enabled
0
RAME0
1
R/W RAM Enable 0 (corresponding area of on-chip RAM
(high-speed): page 0*)
0: Access to on-chip RAM (high-speed) disabled
1: Access to on-chip RAM (high-speed) enabled
Note: * For addresses in each page, see section 31, On-Chip RAM.
Rev. 2.00 Mar. 14, 2008 Page 1566 of 1824
REJ09B0290-0200