SH7263 Datasheet, PDF (1377/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 25 USB 2.0 Host/Function Module (USB)
Table 25.22 Timing at which BRDY Interrupts are Generated
Register setting
Buffer State
When Packet is Received
BFRE = 0
BFRE = 1
Buffer full (normal packet received) When packet is received Not generated
Zero-length packet received
When packet is received When packet is received
Normal short packet received
When packet is received
When reading of the received
data from the buffer memory
has been completed
Transaction count ended
When packet is received
When reading of the received
data from the buffer memory
has been completed
Note: This function is valid only in the reading direction of reading from the buffer memory. In the
writing direction, the BFRE bit should be fixed at 0.
(4) Timing at which the FIFO Port can be Accessed
(a) Timing at which the FIFO Port can be Accessed when Switching Pipes
Figure 25.15 shows a diagram of the timing up to the point where the FRDY and DTLN bits are
determined when the pipe specified by the FIFO port has been switched (the CURPIPE bit in
C/DnFIFOSEL has been changed).
If the CURPIPE bits have been changed, access to the FIFO port should be carried out after
waiting 450 ns and 8 clock cycles at a peripheral clock after writing to C/DnFIFOSEL.
The same timing applies with respect to the CFIFO port, when the ISEL bit is changed.
Rev. 2.00 Mar. 14, 2008 Page 1343 of 1824
REJ09B0290-0200