SH7263 Datasheet, PDF (315/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 9 Bus State Controller (BSC)
9.4.4 SDRAM Control Register (SDCR)
SDCR specifies the method to refresh and access SDRAM, and the types of SDRAMs to be
connected.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
-
-
-
-
-
-
-
-
-
-
A2ROW[1:0]
-
A2COL[1:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R R/W R/W R R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
- DEEP SLOW RFSH RMODEPDOWN BACTV -
-
-
A3ROW[1:0]
-
A3COL[1:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R R/W R/W R/W R/W R/W R/W R
R
R R/W R/W R R/W R/W
Bit
Bit Name
31 to 21 ⎯
Initial
Value
All 0
20, 19 A2ROW[1:0] 00
18
⎯
0
17, 16 A2COL[1:0] 00
R/W Description
R
Reserved
These bits are always read as 0. The write value
should always be 0.
R/W Number of Bits of Row Address for Area 2
Specify the number of bits of row address for area 2.
00: 11 bits
01: 12 bits
10: 13 bits
11: Reserved (setting prohibited)
R
Reserved
This bit is always read as 0. The write value should
always be 0.
R/W Number of Bits of Column Address for Area 2
Specify the number of bits of column address for
area 2.
00: 8 bits
01: 9 bits
10: 10 bits
11: Reserved (setting prohibited)
Rev. 2.00 Mar. 14, 2008 Page 281 of 1824
REJ09B0290-0200