SH7263 Datasheet, PDF (1075/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 20 IEBus^TM Controller (IEB)
20.3.9 IEBus Reception Master Address Register 1 (IEMA1)
IEMA1 indicates the lower four bits of the communication destination master unit address in
slave/broadcast reception.
Bit: 7
6
5
4
3
2
1
0
IMAL4
-
-
-
-
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
Bit
7 to 4
3 to 0
Initial
Bit Name Value R/W
IMAL4
0000 R
⎯
All 0 R
Description
Lower Four Bits of IEBus Reception Master Address
Indicates the lower four bits of the communication
destination master unit address in slave/broadcast
reception. This register is enabled when
slave/broadcast reception starts, and the contents are
changed at the time of setting the RXS flag. If a
broadcast receive error interrupt is selected by the DEE
bit in IECTR and the receive buffer is not in the receive
enabled state at control field reception, a receive error
interrupt is generated and the lower four bits of the
master address are stored in IEMA1.
Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 2.00 Mar. 14, 2008 Page 1041 of 1824
REJ09B0290-0200