SH7263 Datasheet, PDF (1234/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 24 AND/NAND Flash Memory Controller (FLCTL)
24.3.5 Address Register 2 (FLADR2)
FLADR2 is a 32-bit readable/writable register, and is valid when the ADRCNT2 bit in
FLCMDCR is set to 1. FLADR2 specifies an address to be output in command access mode.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit: 15 14 13 12 11 10 9
-
-
-
-
-
-
-
Initial value: 0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
8
7
6
5
4
3
2
1
0
-
ADR5[7:0]
0
0
0
0
0
0
0
0
0
R R/W R/W R/W R/W R/W R/W R/W R/W
Initial
Bit
Bit Name Value R/W
31 to 8 —
All 0 R
7 to 0 ADR5[7:0] All 0 R/W
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Fifth Address Data
Specify 5th data to be output to flash memory as an
address when ADRMD = 1.
Rev. 2.00 Mar. 14, 2008 Page 1200 of 1824
REJ09B0290-0200