SH7263 Datasheet, PDF (1205/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 22 A/D Converter (ADC)
22.5 Interrupt Sources and DMAC Transfer Request
The A/D converter generates an A/D conversion end interrupt (ADI) at the end of A/D conversion.
An ADI interrupt request is generated if the ADIE bit is set to 1 when the ADF bit in ADCSR is
set to 1 on completion of A/D conversion. Note that the direct memory access controller (DMAC)
can be activated by an ADI interrupt depending on the DMAC setting. In this case, an interrupt is
not issued to the CPU. If the setting to activate the DMAC has not been made, an interrupt request
is sent to the CPU. Having the converted data read by the DMAC in response to an ADI interrupt
enables continuous conversion to be achieved without imposing a load on software.
In single mode, set the DMAC so that DMA transfer initiated by an ADI interrupt is performed
only once. In the case of A/D conversion on multiple channels in scan mode or multi mode, setting
the DMA transfer count to one causes DMA transfer to finish after transferring only one channel
of data. To make the DMAC transfer all conversion data, set the ADDR where A/D conversion
data is stored as the transfer source address, set the number of converted channels as the transfer
count, and set the TC bit in the DMA channel control register (CHCR) to 1.
When the DMAC is activated by ADI, the ADF bit in ADCSR is automatically cleared to 0 when
data is transferred by the DMAC.
Table 22.6 Relationship between Interrupt Sources and DMAC Transfer Request
Name
ADI
Interrupt Source
A/D conversion end
Interrupt Flag
ADF in ADCSR
DMAC Activation
Possible
Rev. 2.00 Mar. 14, 2008 Page 1171 of 1824
REJ09B0290-0200