SH7263 Datasheet, PDF (228/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 7 User Break Controller (UBC)
7.3.2 Break Address Mask Register (BAMR)
BAMR is a 32-bit readable/writable register. BAMR specifies bits masked in the break address
bits specified by BAR.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BAM31 BAM30 BAM29 BAM28 BAM27 BAM26 BAM25 BAM24 BAM23 BAM22 BAM21 BAM20 BAM19 BAM18 BAM17 BAM16
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
BAM15 BAM14 BAM13 BAM12 BAM11 BAM10 BAM9 BAM8 BAM7 BAM6 BAM5 BAM4 BAM3 BAM2 BAM1 BAM0
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit
31 to 0
Bit Name
BAM31 to
BAM0
Initial
Value
All 0
R/W Description
R/W Break Address Mask
Specify bits masked in the break address bits specified
by BAR (BA31 to BA0).
0: Break address bit BAn is included in the break
condition
1: Break address bit BAn is masked and not included
in the break condition
Note: n = 31 to 0
Rev. 2.00 Mar. 14, 2008 Page 194 of 1824
REJ09B0290-0200