SH7263 Datasheet, PDF (95/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 2 CPU
2.4 Instruction Set
2.4.1 Instruction Set by Classification
Table 2.10 lists the instructions according to their classification.
Table 2.10 Classification of Instructions
Operation
Classification Types Code
Function
No. of
Instructions
Data transfer 13
MOV
Data transfer
62
Immediate data transfer
Peripheral module data transfer
Structure data transfer
Reverse stack transfer
MOVA
Effective address transfer
MOVI20 20-bit immediate data transfer
MOVI20S 20-bit immediate data transfer
8-bit left-shit
MOVML R0–Rn register save/restore
MOVMU Rn–R14 and PR register save/restore
MOVRT T bit inversion and transfer to Rn
MOVT
T bit transfer
MOVU Unsigned data transfer
NOTT
T bit inversion
PREF
Prefetch to operand cache
SWAP
Swap of upper and lower bytes
XTRCT Extraction of the middle of registers connected
Rev. 2.00 Mar. 14, 2008 Page 61 of 1824
REJ09B0290-0200