SH7263 Datasheet, PDF (524/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
11.3.11 Timer Counter (TCNT)
The TCNT counters are 16-bit readable/writable counters. The MTU2 has five TCNT counters,
one each for channels 0 to 4.
The TCNT counters must not be accessed in eight bits; they should always be accessed in 16 bits.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Note: The TCNT counters must not be accessed in eight bits; they should always be accessed in 16 bits.
11.3.12 Timer General Register (TGR)
The TGR registers are 16-bit readable/writable registers. The MTU2 has eighteen TGR registers,
six for channel 0, two each for channels 1 and 2, four each for channels 3 and 4.
TGRA, TGRB, TGRC, and TGRD function as either output compare or input capture registers.
TGRC and TGRD for channels 0, 3, and 4 can also be designated for operation as buffer registers.
TGR buffer register combinations are TGRA and TGRC, and TGRB and TGRD.
TGRE_0 and TGRF_0 function as compare registers. When the TCNT_0 count matches the
TGRE_0 value, an A/D converter start request can be issued. TGRF can also be designated for
operation as a buffer register. TGR buffer register combination is TGRE and TGRF.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
Initial value: 1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Note: The TGR registers must not be accessed in eight bits; they should always be accessed in 16 bits.
TGR registers are initialized to H'FFFF.
Rev. 2.00 Mar. 14, 2008 Page 490 of 1824
REJ09B0290-0200