SH7263 Datasheet, PDF (975/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 19 Controller Area Network (RCAN-TL1)
TSEG2:
TSG2 + 1
The RCAN-TL1 Bit Rate Calculation is:
Bit Rate =
fclk
2 × (BRP + 1) × (TSEG1 + TSEG2 + 1)
Where BRP is given by the register value and TSEG1 and TSEG2 are derived values from TSG1
and TSG2 register values. The ‘+1’ in the above formula is for the Sync-Seg which duration is 1
time quanta.
f_CLK = Peripheral Clock
BCR Setting Constraints
TSEG1min > TSEG2 ≥ SJWmax (SJW = 1 to 4)
8 < TSEG1 + TSEG2 + 1 < 25 time quanta (TSEG1 + TSEG2 + 1 = 7 is not allowed)
TSEG2 > 2
These constraints allow the setting range shown in the table below for TSEG1 and TSEG2 in the
Bit Configuration Register. The number in the table shows possible setting of SJW. "No" shows
that there is no allowed combination of TSEG1 and TSEG2.
Rev. 2.00 Mar. 14, 2008 Page 941 of 1824
REJ09B0290-0200