SH7263 Datasheet, PDF (1825/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Main Revisions for this Edition
Item
16.4.5 SSU Mode
(2) Data Transmission
Page
806
Figure 16.5 Example of 807
Transmission Operation
(SSU Mode)
Revision (See Manual for Details)
Description amended
… At this time, if the TIE bit in SSER is set to 1, a transmit-
data-empty SSTXI interrupt is generated.
When 1-frame data has been transferred with TDRE = 0, the
SSTDR contents are transferred to SSTRSR to start the next
frame transmission. When the 8th bit of transmit data has been
transferred with TDRE = 1, the TEND bit in SSSR is set to 1
and the state is retained. At this time, if the TEIE bit is set to 1,
a transmit-end SSTXI interrupt is generated. After
transmission, the output level of the SSCK pin is fixed high
when CPOS = 0 and low when CPOS = 1.
Figure amended
(1) When 8-bit data length is selected (SSTDR0 is valid) with CPOS = 0 and CPHS = 0
SCS
1 frame
1 frame
SSCK
SSO
TDRE
Bit Bit Bit Bit Bit Bit Bit Bit
01234567
SSTDR0
(LSB first transmission)
Bit Bit Bit Bit Bit Bit Bit Bit
76543210
SSTDR0
(MSB first transmission)
TEND
LSI operation
SSTXI interrupt
generated
User operation Data written to SSTDR0
SSTXI interrupt SSTXI interrupt
generated
generated
Data written to SSTDR0
SSTXI interrupt
generated
(2) When 16-bit data length is selected (SSTDR0 and SSTDR1 are valid) with CPOS = 0 and CPHS = 0
SCS
1 frame
SSCK
SSO
(LSB first)
SSO
(MSB first)
TDRE
Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit
0123456701234567
SSTDR1
SSTDR0
Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit
76543210 76543210
SSTDR0
SSTDR1
TEND
LSI operation
SSTXI interrupt generated
User operation Data written to SSTDR0 and SSTDR1
SSTXI interrupt generated
(3) When 32-bit data length is selected (SSTDR0 to SSTDR3 are valid) with CPOS = 0 and CPHS = 0
SCS
1 frame
SSCK
SSO
(LSB first)
SSO
(MSB first)
TDRE
Bit _to Bit
0
7
SSTDR 3
Bit _to Bit
0
7
SSTDR2
Bit _to Bit
0
7
SSTDR1
Bit _to Bit
0
7
SSTDR0
Bit _to Bit
7
0
SSTDR0
Bit _to Bit
7
0
SSTDR1
Bit _to Bit
7
0
SSTDR2
Bit _to Bit
7
0
SSTDR3
TEND
LSI operation
SSTXI interrupt generated SSTXI interrupt generated
User operation Data written to SSTDR0 to SSTDR3
Rev. 2.00 Mar. 14, 2008 Page 1791 of 1824
REJ09B0290-0200