SH7263 Datasheet, PDF (909/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 18 Serial Sound Interface (SSI)
Initial
Bit
Bit Name Value R/W Description
11
SPDP
0
R/W Serial Padding Polarity
0: Padding bits are low.
1: Padding bits are high.
Note: When MUEN is 1, the padding bits are driven low
(the mule function is given priority).
10
SDTA
0
R/W Serial Data Alignment
0: Transmitting and receiving in the order of serial data
and padding bits
1: Transmitting and receiving in the order of padding
bits and serial data
9
PDTA
0
R/W Parallel Data Alignment
This bit is ignored if CPEN = 1. When the data word
length is 32, 16 or 8 bit, this configuration field has no
meaning.
This bit applies to SSIRDR in receive mode and
SSITDR in transmit mode.
0: Parallel data (SSITDR, SSIRDR) is left-aligned
1: Parallel data (SSITDR, SSIRDR) is right-aligned.
• DWL = 000 (with a data word length of 8 bits), the
PDTA setting is ignored.
All data bits in SSIRDR or SSITDR are used on the
audio serial bus. Four data words are transmitted or
received at each 32-bit access. The first data word
is derived from bits 7 to 0, the second from bits 15
to 8, the third from bits 23 to 16 and the last data
word is derived from bits 31 to 24.
• DWL = 001 (with a data word length of 16 bits), the
PDTA setting is ignored.
All data bits in SSIRDR or SSITDR are used on the
audio serial bus. Two data words are transmitted or
received at each 32-bit access. The first data word
is derived from bits 15 to 0 and the second data
word is derived from bits 31 to 16.
Rev. 2.00 Mar. 14, 2008 Page 875 of 1824
REJ09B0290-0200