SH7263 Datasheet, PDF (1233/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 24 AND/NAND Flash Memory Controller (FLCTL)
• ADRMD = 0
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
-
-
-
-
-
ADR[25:16]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15
Initial value: 0
R/W: R/W
14
0
R/W
13
0
R/W
12
0
R/W
11
0
R/W
10
0
R/W
9
0
R/W
8
7
ADR[15:0]
0
0
R/W R/W
6
0
R/W
5
0
R/W
4
0
R/W
3
0
R/W
2
0
R/W
1
0
R/W
0
0
R/W
Initial
Bit
Bit Name Value R/W
31 to 26 —
All 0 R
25 to 0 ADR[25:0] All 0 R/W
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Sector Address Specification
Specify a sector number to be accessed when ADRMD
= 0. The sector number is converted into an address
and is output to flash memory.
When the ADRCNT2 bit in FLCMDCR = 1, the
ADR[25:0] bits are valid. When the ADRCNT2 bit in
FLCMDCR = 0, the ADR[17:0] bits are valid. For
details, see figure 24.15.
• Large-block products (2048 + 64 bytes)
ADR[25:2] specifies the page address and ADR[1:0]
specifies the column address in sector units.
ADR[1:0] = 00: 0th byte (sector 0)
ADR[1:0] = 01: (512 + 16)th byte (sector 1)
ADR[1:0] = 10: (1024 + 32)th byte (sector 2)
ADR[1:0] = 11: (1536 + 48)th byte (sector 3)
• Small-block products (512 + 16 bytes)
Only the page address can be specified.
Rev. 2.00 Mar. 14, 2008 Page 1199 of 1824
REJ09B0290-0200