SH7263 Datasheet, PDF (265/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 9 Bus State Controller (BSC)
Section 9 Bus State Controller (BSC)
The bus state controller (BSC) outputs control signals for various types of memory and external
devices that are connected to the external address space. BSC functions enable this LSI to connect
directly with SRAM, SDRAM, and other memory storage devices, and external devices.
9.1 Features
1. External address space
⎯ A maximum of 64 Mbytes for each of areas CS0 to CS7.
⎯ Can specify the normal space interface, SRAM interface with byte selection, burst ROM
(clocked synchronous or asynchronous), MPX-I/O, burst MPX-I/O, SDRAM, and
PCMCIA interface for each address space.
⎯ Can select the data bus width (8, 16, or 32 bits) for each address space.
⎯ Controls insertion of wait cycles for each address space.
⎯ Controls insertion of wait cycles for each read access and write access.
⎯ Can set independent idle cycles during the continuous access for five cases: read-write (in
same space/different spaces), read-read (in same space/different spaces), the first cycle is a
write access.
2. Normal space interface
⎯ Supports the interface that can directly connect to the SRAM.
3. Burst ROM interface (clocked asynchronous)
⎯ High-speed access to the ROM that has the page mode function.
4. MPX-I/O interface
⎯ Can directly connect to a peripheral LSI that needs an address/data multiplexing.
5. SDRAM interface
⎯ Can set the SDRAM in up to two areas.
⎯ Multiplex output for row address/column address.
⎯ Efficient access by single read/single write.
⎯ High-speed access in bank-active mode.
⎯ Supports an auto-refresh and self-refresh.
⎯ Supports low-frequency and power-down modes.
⎯ Issues MRS and EMRS commands.
Rev. 2.00 Mar. 14, 2008 Page 231 of 1824
REJ09B0290-0200