SH7263 Datasheet, PDF (1094/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 20 IEBus^TM Controller (IEB)
Initial
Bit
Bit Name Value R/W Description
3
RXEOVEE 0
R/W Overrun Control Flag Interrupt Enable
Enables/disables an overrun control flag (RXEOVE)
interrupt
0: Disables an overrun control flag (RXEOVE) interrupt
1: Enables an overrun control flag (RXEOVE) interrupt
2
RXERTMEE 0
R/W Receive Timing Error Interrupt Enable
Enables/disables a receive timing error (RXERTME)
interrupt.
0: Disables a receive timing error (RXERTME) interrupt
1: Enables a receive timing error (RXERTME) interrupt
1
RXEDLEE 0
R/W Overflow of Maximum Number of Receive Bytes in One
Frame Interrupt Enable
Enables/disables an overflow of the maximum number of
receive bytes in one frame (RXEDLE) interrupt
0: Disables an overflow of the maximum number of
receive bytes in one frame (RXEDLE) interrupt
1: Enables an overflow of the maximum number of
receive bytes in one frame (RXEDLE) interrupt
0
RXEPEE 0
R/W Parity Error Interrupt Enable
Enables/disables a parity error (RXEPE) interrupt
0: Disables a parity error (RXEPE) interrupt
1: Enables a parity error (RXEPE) interrupt
20.3.20 IEBus Clock Selection Register (IECKSR)
IECKSR is a readable/writable 8-bit register that specifies the clock used in IEB.
Bit: 7
6
5
4
3
2
1
0
-
-
- CKS3 -
CKS[2:0]
Initial value: 0
0
0
0
0
0
0
1
R/W: R R R R/W R R/W R/W R/W
Rev. 2.00 Mar. 14, 2008 Page 1060 of 1824
REJ09B0290-0200