SH7263 Datasheet, PDF (772/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 15 Serial Communication Interface with FIFO (SCIF)
Table 15.4 lists the sample SCBRR settings in asynchronous mode in which a base clock
frequency is 16 times the bit rate (the ABCS bit in SCEMR is 0) and the baud rate generator
operates in normal mode (the BGDM bit in SCEMR is 1), and table 15.5 lists the sample SCBRR
settings in clock synchronous mode.
Table 15.4 Bit Rates and SCBRR Settings (Asynchronous Mode, BGDM = 0, ABCS = 0) (1)
Bit
Rate
(bit/s) _n
110 2
150 2
300 1
600 1
1200 0
2400 0
4800 0
9600 0
19200 0
31250 0
38400 0
8
Error
N
(%) n
141 0.03 2
103 0.16 2
207 0.16 1
103 0.16 1
207 0.16 0
103 0.16 0
51 0.16 0
25 0.16 0
12 0.16 0
7
0.00 0
6
−6.99 0
Pφ (MHz)
9.8304
Error
N
(%) n
174 −0.26 2
127 0.00 2
255 0.00 2
127 0.00 1
255 0.00 1
127 0.00 0
63 0.00 0
31 0.00 0
15 0.00 0
9
−1.70 0
7
0.00 0
10
N
177
129
64
129
64
129
64
32
15
9
7
Error
(%) n
−0.25 2
0.16 2
0.16 2
0.16 1
0.16 1
0.16 0
0.16 0
−1.36 0
1.73 0
0.00 0
1.73 0
12
N
212
155
77
155
77
155
77
38
19
11
9
Error
(%)
0.03
0.16
0.16
0.16
0.16
0.16
0.16
0.16
0.16
0.00
−2.34
Rev. 2.00 Mar. 14, 2008 Page 738 of 1824
REJ09B0290-0200