SH7263 Datasheet, PDF (1089/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 20 IEBus^TM Controller (IEB)
20.3.18 IEBus Receive Status Register (IERSR)
IERSR detects receive busy, receive start, receive normal completion, or receive completion with
an error. Each status flag in IERSR corresponds to a bit in the IEIER that enables/disables each
interrupt. This register is cleared by writing 1 to each bit.
Bit: 7
6
5
4
3
2
1
0
RXBSY RXS
RXF
RXEDE RXEOVE
RXE
RTME
RXEDLE RXEPE
Initial value: 0
0
0
0
0
0
0
0
R/W: R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)*
Initial
Bit
Bit Name Value R/W Description
7
RXBSY
1
R/(W)* Receive Busy
Indicates that the receive data is stored in the receive
data buffer (IERB001 to IERB128). Clear this bit after
reading out all data. The next receive data cannot be
received while this bit is set.
[Setting condition]
• When all receive data has been written to the
receive data buffer.
[Clearing condition]
• When 1 is written
6
RXS
0
R/(W)* Receive Start Detection
Indicates that the IEB starts reception.
[Setting conditions]
• When the data from the master unit to message
length field has been received correctly in slave
reception
[Clearing condition]
• When 1 is written
Rev. 2.00 Mar. 14, 2008 Page 1055 of 1824
REJ09B0290-0200