SH7263 Datasheet, PDF (1331/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 25 USB 2.0 Host/Function Module (USB)
25.3.35 Pipe Timing Control Register (PIPEPERI)
PIPEPERI is a register that selects whether the buffer is flushed or not when an interval error
occurred during isochronous IN transfer, and sets the interval error detection interval for PIPE1
and PIPE2.
This register is initialized by a power-on reset or a software reset.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
IFIS
-
-
-
-
-
-
-
-
-
IITV[2:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R R/W R
R
R
R
R
R
R
R
R R/W R/W R/W
Bit
Bit Name
15 to 13 ⎯
12
IFIS
Initial
Value R/W
All 0 R
0
R/W
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Isochronous IN Buffer Flush
0: The buffer is not flushed
1: The buffer is flushed
This bit is valid only when isochronous transfer is
selected. Before using this bit, the following settings
are required:
• When isochronous-IN transfer is started
(1) Set the IFIS bit to 1.
(2) Set the PID1 and PID0 bits in PIPEnCTR to
01 (BUF).
(3) Write transmit data to the Iso-IN PIPE FIFO
buffer.
When the IFIS bit is not used for transfer, the above
procedures are not required.
• When isochronous-IN transfer is ended
(1) Clear the PID1 and PID0 bits to 00 (NAK).
(2) Set the ACLRM bit in PIPEnCTR to 1.
(3) Wait at least 100 ns.
(4) Clear the ACLRM bit to 0.
When the IFIS bit is not used for transfer, ACLRM
setting is not required.
Rev. 2.00 Mar. 14, 2008 Page 1297 of 1824
REJ09B0290-0200