SH7263 Datasheet, PDF (143/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 4 Clock Pulse Generator (CPG)
4.4 Register Descriptions
The clock pulse generator has the following registers.
Table 4.4 Register Configuration
Register Name
Frequency control register
Abbreviation R/W
FRQCR
R/W
Initial Value Address Access Size
H'0003
H'FFFE0010 16
4.4.1 Frequency Control Register (FRQCR)
FRQCR is a 16-bit readable/writable register used to specify whether a clock is output from the
CKIO pin during normal operation mode, release of bus mastership, software standby mode and
standby mode cancellation. The register also specifies the frequency-multiplier of the PLL circuit
and the frequency division ratio for the internal clock and peripheral clock (Pφ). FRQCR is
accessed by word.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
- CKOEN2 CKOEN[1:0]
-
-
STC[1:0]
-
-
-
IFC
-
PFC[2:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
R/W: R R/W R/W R/W R
R R/W R/W R
R
R R/W R R/W R/W R/W
Initial
Bit
Bit Name Value R/W Description
15
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
Rev. 2.00 Mar. 14, 2008 Page 109 of 1824
REJ09B0290-0200