SH7263 Datasheet, PDF (1129/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 21 CD-ROM Decoder (ROM-DEC)
21.3.6 Decoding Option Setting Control Register (CROMCTL4)
The decoding option setting control register (CROMCTL4) enables/disables buffering control at
link block detection, specifies the information indicated by the status register, and controls the
ECC correction mode. The setting of this register becomes valid at the sector-to-sector transition
Bit: 7
6
LINKOFF LINK2
Initial value: 0
0
R/W: R/W R/W
5
4
3
2
- ER0SEL NO_ECC -
0
0
0
0
R/W R/W R/W R/W
1
-
0
R/W
0
-
0
R/W
Initial
Bit Bit Name Value
7
LINKOFF 0
6
LINK2
0
5
⎯
0
R/W Description
R/W Buffering Control at Link Block Detection
0: ON
1: OFF
When this bit is set to 1, buffering control is not
performed when a link block is detected. The link block
is processed as normal sectors.
However, link-block detection processing does proceed,
and the results are reflected in the values of bits 3 to 0
in the CROMST5 register.
R/W Link Block Detection Condition
0: The block is regarded as a link block when either run-
out 1 or 2 and both run-in 3 and 4 have been
detected.
1: The block is regarded as a link block when two out of
run-out 1 and 2 and “link” have been detected.
When this bit is set to 1, buffering control for link blocks
is disabled (link blocks are processed as normal
sectors). The condition for setting of the LINK_ON bit in
CROMST5 is decoding of the link sector.
R/W Reserved
This bit is always read as 0. The write value should
always be 0.
Rev. 2.00 Mar. 14, 2008 Page 1095 of 1824
REJ09B0290-0200