SH7263 Datasheet, PDF (1299/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 25 USB 2.0 Host/Function Module (USB)
25.3.15 BEMP Interrupt Enabled Register (BEMPENB)
BEMPENB is a register that enables BEMP interrupts for each pipe.
This register is initialized by a power-on reset or a software reset.
Bit: 15 14 13 12 11 10 9
-
-
-
-
-
-
-
Initial value: 0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
8
7
6
5
4
3
2
1
0
-
PIPE7 PIPE6 PIPE5 PIPE4 PIPE3 PIPE2 PIPE1 PIPE0
BEMPE BEMPE BEMPE BEMPE BEMPE BEMPE BEMPE BEMPE
0
0
0
0
0
0
0
0
0
R R/W R/W R/W R/W R/W R/W R/W R/W
Bit
Bit Name
15 to 8 ⎯
Initial
Value
All 0
7
PIPE7BEMPE 0
6
PIPE6BEMPE 0
5
PIPE5BEMPE 0
4
PIPE4BEMPE 0
3
PIPE3BEMPE 0
R/W
R
R/W
R/W
R/W
R/W
R/W
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
BEMP Interrupt Enable for PIPE7
0: Interrupt output disabled
1: Interrupt output enabled
BEMP Interrupt Enable for PIPE6
0: Interrupt output disabled
1: Interrupt output enabled
BEMP Interrupt Enable for PIPE5
0: Interrupt output disabled
1: Interrupt output enabled
BEMP Interrupt Enable for PIPE4
0: Interrupt output disabled
1: Interrupt output enabled
BEMP Interrupt Enable for PIPE3
0: Interrupt output disabled
1: Interrupt output enabled
Rev. 2.00 Mar. 14, 2008 Page 1265 of 1824
REJ09B0290-0200