SH7263 Datasheet, PDF (961/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 19 Controller Area Network (RCAN-TL1)
TXPRI
MBI is under transmission
TXPRI is kept set in Time Trigger Mode
TXACKI
ABACKI
Both TXACKI and ABACKI
are set without clearing TXACKI
TXCRI
cancellation is accepted
Figure 19.7 TXACK and ABACK in Time Trigger Transmission
Please note that for Mailbox 30 TTW is fixed to ‘01’, Offset to ‘00’ and rep_factor to ‘0’.The
following tables report the combinations for the rep_factor and the offset.
Rep_factor
3'b000
3'b001
3'b010
3'b011
3'b100
3'b101
3'b110
3'b111
Description
Every basic cycle (initial value)
Every two basic cycle
Every four basic cycle
Every eight basic cycle
Every sixteen basic cycle
Every thirty two basic cycle
Every sixty four basic cycle (once in system matrix)
Reserved
The Offset Field determines the first cycle in which a Time Triggered Mailbox may start
transmitting its Message.
Rev. 2.00 Mar. 14, 2008 Page 927 of 1824
REJ09B0290-0200