SH7263 Datasheet, PDF (48/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 1 Overview
Classification
Operating mode
control
System control
Symbol
I/O Name
Function
MD
I
Mode set
Sets the operating mode. Do not
change the signal level on this pin
during operation.
MD_CLK1, I
MD_CLK0
ASEMD
I
Clock mode set
ASE mode
These pins set the clock operating
mode. Do not change the signal
levels on these pins during
operation.
If a low level is input at the ASEMD
pin while the RES pin is asserted,
ASE mode is entered; if a high level
is input, product chip mode is
entered.
In ASE mode, the E10A-USB
emulator function is enabled. When
this function is not in use, fix it high.
RES
I
Power-on reset This LSI enters the power-on reset
state when this signal goes low.
MRES
I
Manual reset
This LSI enters the manual reset
state when this signal goes low.
WDTOVF O Watchdog timer Outputs an overflow signal from the
overflow
WDT.
BREQ
I
Bus-mastership A low level is input to this pin when
request
an external device requests the
release of the bus mastership.
BACK
O Bus-mastership Indicates that the bus mastership
request
acknowledge
has been released to an external
device. Reception of the BACK
signal informs the device which has
output the BREQ signal that it has
acquired the bus.
Rev. 2.00 Mar. 14, 2008 Page 14 of 1824
REJ09B0290-0200