SH7263 Datasheet, PDF (787/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 15 Serial Communication Interface with FIFO (SCIF)
15.3.12 Line Status Register (SCLSR)
The CPU can always read or write to SCLSR, but cannot write 1 to the ORER flag. This flag can
be cleared to 0 only if it has first been read (after being set to 1).
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
- ORER
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R R/(W)*
Note: * Only 0 can be written to clear the flag after 1 is read.
Bit
15 to 1
Bit Name
—
0
ORER
Initial
Value
All 0
0
R/W Description
R
Reserved
These bits are always read as 0. The write value
should always be 0.
R/(W)* Overrun Error
Indicates the occurrence of an overrun error.
0: Receiving is in progress or has ended normally*¹
[Clearing conditions]
• ORER is cleared to 0 when the chip is a power-on
reset
• ORER is cleared to 0 when 0 is written after 1 is
read from ORER.
1: An overrun error has occurred*²
[Setting condition]
• ORER is set to 1 when the next serial receiving is
finished while the receive FIFO is full of 16-byte
receive data.
Notes: 1. Clearing the RE bit to 0 in SCSCR does
not affect the ORER bit, which retains its
previous value.
2. The receive FIFO data register
(SCFRDR) retains the data before an
overrun error has occurred, and the next
received data is discarded. When the
ORER bit is set to 1, the SCIF cannot
continue the next serial reception.
Rev. 2.00 Mar. 14, 2008 Page 753 of 1824
REJ09B0290-0200