SH7263 Datasheet, PDF (1554/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 30 I/O Ports
30.2 Port A
Port A is an input/output port with eight pins as shown in figure 30.1.
Port A
PA7 (input) / AN7 (input) / DA1 (output)
PA6 (input) / AN6 (input) / DA0 (output)
PA5 (input) / AN5 (input)
PA4 (input) / AN4 (input)
PA3 (input) / AN3 (input)
PA2 (input) / AN2 (input)
PA1 (input) / AN1 (input)
PA0 (input) / AN0 (input)
Figure 30.1 Port A
30.2.1 Register Descriptions
Table 30.1 lists the port A registers.
Table 30.1 Register Configuration
Register Name
Abbreviation R/W
Port A data register L PADRL
R
Initial Value Address
Access Size
H'00xx
H'FFFE3802 8, 16
30.2.2 Port A Data Register L (PADRL)
PADRL is a 16-bit read-only register that stores port A data. The PA7DR to PA0DR bits
correspond to the PA7/AN7/DA1 to PA0/AN0 pins, respectively. The general input function of
the PA7 to PA0 pins is enabled only when the A/D and D/A converters are halted.
Writing to these bits is ignored, and therefore does not affect the pin state. If these bits are read,
the pin state, not the bit value, is directly returned. Note that, however, this register should not be
read during operation of the A/D or D/A converter. Table 30.2 summarizes PADRL read/write
operation.
Bit: 15 14 13 12 11 10 9
-
-
-
-
-
-
-
Initial value: 0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
Note: * Depends on the state of the external pin.
8
7
6
5
4
3
2
1
0
-
PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0
DR DR DR DR DR DR DR DR
0
*
*
*
*
*
*
*
*
R
R
R
R
R
R
R
R
R
Rev. 2.00 Mar. 14, 2008 Page 1520 of 1824
REJ09B0290-0200