SH7263 Datasheet, PDF (461/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 10 Direct Memory Access Controller (DMAC)
Figure 10.6 shows an example of DMA transfer timing in dual address mode.
CKIO
A25 to A0
CSn
Transfer source
address
Transfer destination
address
D31 to D0
RD
WEn
DACKn
(Active-low)
Data read cycle
(1st cycle)
Data write cycle
(2nd cycle)
Note: In transfer between external memories, with DACK output in the read cycle,
DACK output timing is the same as that of CSn.
Figure 10.6 Example of DMA Transfer Timing in Dual Mode
(Transfer Source: Normal Memory, Transfer Destination: Normal Memory)
Rev. 2.00 Mar. 14, 2008 Page 427 of 1824
REJ09B0290-0200